Dynamically calibrating the impedance of an output driver on an integrated circuit can have several advantages. It can reduce reflections on the output signal, reduce electromagnetic interference (EMI), reduce power dissipation, and reduce signal skew.
On a CMOS integrated circuit (IC), one way of controlling the impedance of an output driver is to split the pull-up transistor (typically a p-channel MOSFET (PFET) with it's source connected to the positive supply, VDD) and the pull-down transistor (typically a n-channel MOSFET (NFET) with it's source connected to the negative supply, GND) into multiple transistors. When the output driver is driving, each of these multiple transistors is then appropriately controlled to turn on, or remain off, according to a set of calibration signals such that the desired output impedance is achieved. Since the pull-up and pull-down transistors typically have different conductance and are sized differently, they usually require different sets of calibration signals. Normally, to generate these two set of calibration signals, two external resistors are used (one for the pull-up FETs and one for the pull-down FETs). This uses two calibration pins for each section of the chip that requires a different drive impedance. Since prudence would suggest having differently calibrated drivers for each side of the chip to compensate for process, voltage, and temperature fluctuations across a die as well as a different impedance for each type of signal, or group of signals, a large number of pins may have to be used as calibration pins. This increases the cost of the chip, and the assembly cost of any board the chip is used on.
Accordingly there is a need in the art for a way to reduce the number of calibration pins required for an impedance controlled CMOS output driver.